1. Field of the Invention
The present invention relates to liquid crystal displays, and more particularly to a liquid crystal display capable of improving a picture quality.
2. Discussion of the Related Art
Generally, pictures arc displayed by liquid crystal displays (LCDs) by receiving video data signals and selectively controlling light transmittance characteristics of liquid crystal cells arranged in a matrix pattern within a liquid crystal display panel. Owing to their light weight, minimized thickness, and low power consumption, LCDs are finding uses in an increasing number of applications. Particularly, chip-on-glass (COG) type LCDs include LSI driver integrated circuits (ICs) mounted on liquid crystal display panels. Electrical conductors used to apply signals to driver ICs of COG-type LCDs are fabricated directly on a lower glass substrate using a line-on-glass (LOG) technique.
FIG. 1 illustrates a schematic view of a COG-type LCD fabricated using an LOG technique.
Referring to FIG. 1, an LCD includes a liquid crystal display panel 2 having a plurality of pixels are arranged in a matrix pattern, a plurality of data driver ICs 8 for supplying data signals to a plurality of data lines DL arranged in the liquid crystal display panel 2, and a plurality of gate driver ICs 12 for supplying gate signals to a plurality of gate lines GL also arranged in the liquid crystal display panel 2.
The liquid crystal display panel 2 further includes lower and upper glass substrates 1a and 1b, respectively, connected to and separated from each other by a layer of liquid crystal material (not shown). The plurality of gate and data lines are formed on the lower glass substrate 1a so as to cross each other. Referring to FIG. 2, a plurality of thin film transistors (TFTs) are formed where the gate and data lines cross each other and selectively supply the video data signals applied to the data lines DL to the liquid crystal cells Clc. Accordingly, gate terminals of each of the TFTs are connected to a corresponding gate line GL, source terminals of each of the TFTs are connected to a corresponding one of the data lines DL, and drain electrodes of each of the TFTs are connected to a corresponding pixel electrode within the liquid crystal cell Clc.
Referring back to FIG. 1, the plurality of data driver ICs 8 are mounted on a plurality of data tape carrier packages (TCPs) 10 and electrically connect the plurality of data lines DL on the liquid crystal display panel 2 to a data printed circuit board (PCB) 6. A controller 18 is formed on the data PCB 6 and controls a power supplier (not shown) in addition to the data and gate driver ICs 8 and 12. The controller 18 controls a driving timing of the data and gate driver ICs 8 and 12 and supplies video data signals to the plurality of data driver ICs 8. The power supplier generates driving voltages (e.g., common voltage (Vcom), gate high voltage (Vgh), gate low voltage (Vgl), etc.) necessary for driving the liquid crystal display.
Dot clock signals (Dclk) and video data signals (e.g., red R, green G, blue B video data signals) are inputted from the controller 18 to the plurality of data driver ICs 8. The plurality of data driver ICs 8 latch the video data signals in synchrony with the dot clock signal (Dclk). The latched video data signals are adjusted in accordance with a gamma voltage. The plurality of data driver ICs 8 convert the adjusted video data signals to analog data signals and selectively apply the analog data signals to the plurality of data lines DL.
The plurality of gate driver ICs 12 are mounted on a plurality of gate TCPs 14 and electrically connect the plurality of the gate lines GL to a gate PCB 4. Each of the plurality of gate driver ICs 12 includes a shift register (not shown) for generating scanning pulses in response to gate start pulses (GSP) inputted from the controller 18 and a level shifter (not shown) for shifting a voltage of the scanning pulses to a level suitable for driving each of the liquid crystal cells within the liquid crystal display panel. Accordingly, each of the TFTs responds to the scanning pulses applied to the plurality of gate lines GL by applying the analog data signals to corresponding pixel electrodes of liquid crystal cells Clcs.
Referring to FIG. 3, gate signals necessary for driving the plurality of gate driver ICs 12 included within COG-type LCDs are applied to the gate PCB 4 via the data PCB 6, the data TCP 10, a line resistor 16, and a gate TCP 14. The line resistor 16 is formed on the liquid crystal display panel 2 and has a resistance value of about 100Ω. As the LCD is a COG-type device, gate signals supplied through the line resistor 16 are transmitted to each of the gate driver ICs 12 via the gate PCB 4 without the use of any flexible printed circuit (FPC).
Due to the presence of the line resistor 16, a voltage value of the gate signals reaching the gate driver ICs 12 must be compensated for and increased by a magnitude of ten to several hundreds of times greater than that required by gate signals transmitted through the FPC. Since the controller 18 cannot eliminate any externally generated electromagnetic noise (e.g., electrostatic discharges (ESD), interference by other signals, etc.), gate signals inputted to the gate driver ICs 12 by the controller may be distorted. Accordingly, a picture quality generated by the COG-type LCD may be deteriorated.